(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming self-aligned polysilicon gate field effect transistors.
(2) Background to the Invention and Description of Related Art
Complimentary metal oxide semiconductor(CMOS) field effect transistor(FET) technology involves the formation n-channel FETs(NMOS) and p-channel FETs(PMOS) in combination to form low current, high performance integrated circuits. The complimentary use of NMOS and PMOS devices, typically in the form of a basic inverter device, allows a considerable increase of circuit density of circuit elements by reduction of heat generation. The increase in device density accompanied by the shrinkage of device size has resulted in improved circuit performance and reliability as well as reduced cost. For these reasons CMOS integrated circuits have found widespread use, particularly in digital applications.
The basic MOSFET, whether it be NMOS or PMOS is typically formed by a self-aligned polysilicon gate process. In order to lower the conductivity of the polysilicon gate a transition metal is often alloyed into the upper surface of the polysilicon. The resultant laminar polysilicon/silicide structure is referred to as a polycide gate. Although there are several ways to form a polycide gate, a well known process which is particularly effective in sub-micron MOSFET technology, because of it""s ability to form the silicide on the polysilicon gate while simultaneously forming high quality source/drain contacts, is the salicide (self-aligned silicide) process.
FIG. 1 shows a cross section of a familiar form of an n-channel, self-aligned polysilicon gate MOSFET (metal oxide silicon field effect transistor) 8 formed with STI (shallow trench isolation) 12 on a silicon wafer 10. The silicon oxide filled trenches form the field isolation around the device 8. The polysilicon gate electrode 17 is photolithographically patterned in a polysilicon layer 16 deposited over a thin gate oxide 14 using photoresist. The LDD (lightly doped drain) portions 18 of the source/drain elements are formed by ion implantation, using the gate 16 as a self-aligned mask. Composite sidewall spacers 21 are then formed which, along with the gate electrode 16, provide a mask for a second ion implantation by which the main portions 22 of the source/drain elements are formed. The sidewall 20 spacers consist of a silicon oxide portion 20A and a silicon nitride portion 20B and are formed with a foot 21 with the aid of an additional sacrificial oxide layer over the nitride which is no longer present in the figure. A refractory metal, for example cobalt or titanium, is deposited on the wafer and is reacted with the polysilicon gate and with the exposed source/drain region by an anneal to form a silicide. The un-reacted metal is removed by wet etching leaving the silicide 24 on the silicon surfaces. Selective formation of a silicide simultaneously on the polysilicon gate and source drain regions to form contact regions is the key characteristic of the salicide process.
Processing steps for forming the MOSFET 8, and which are relevant to the present invention are shown in detail in FIGS. 2A through 2D and will now be described. Referring to FIG. 2A, after the STI 12 is formed and a gate oxide 14 has been grown by thermal oxidation of the exposed silicon regions, a polysilicon gate layer 16 is deposited. The polysilicon gate layer 16 is then patterned with photoresist to form a gate electrode. In order to achieve high photolithographic resolution, it is necessary to deposit a thin anti-reflective coating (ARC) 26 over the gate layer 16 before the photoresist 28 is applied and patterned. The ARC 18 absorbs stray radiation reflected from the surface of the polysilicon gate layer during the photoresist patterning exposure, thereby eliminating unwanted exposure at the pattern edges and improving the crispness of the image. An often used ARC material is silicon oxynitride which is deposited on the gate layer 16 by LPCVD (low pressure chemical vapor deposition) to a thickness of a few hundred Angstroms. The photoresist 28 is then deposited and patterned to define a gate electrode. Referring, next to FIG. 2B, the exposed ARC 26 and the polysilicon gate layer 16 are etched by an anisotropic dry (plasma) etching technique, for example reactive ion etching (RIE), stopping in the gate oxide 14, thereby forming a gate electrode 17. The etchants used are selected to provide a high polysilicon-to-silicon oxide selectivity towards the end of the etching process so that the very thin gate oxide 14 is not penetrated and functions as an etch stop. In addition the gate oxide and the STI 12 must also endure an over etch period wherein and residual pockets of polysilicon are removed.
After the polysilicon gate electrode 17 has been patterned, residual photoresist 28 and protective sidewall polymer (not shown) which is formed on the polysilicon walls during etching, is removed either by ashing in an oxygen plasma or by the use of liquid strippers. It remains for the ARC layer 26 to be removed from the top of the polysilicon gate electrode 17.
A common method for removal of the silicon oxynitride ARC 26 is by dipping the wafer 10 into hot H3PO4 which easily removes the ARC without attacking the gate oxide 14. A problem with this method has been found by the present investigator in the formation of short channel MOSFETs, wherein the hot H3PO4 causes an undercutting 29 of the polysilicon gate electrode, which is shown in the cross section in FIG. 2C. This not only degrades the critical width dimension of the gate electrode but also causes stresses after LDD sidewalls are formed. Referring to FIG. 2D, the completed MOSFET 8 with the undercut gate electrode 17 is shown after composite footed sidewalls 20 and the salicide regions 24 have been formed. Stresses in the sidewalls 20, particularly at the point where the foot is joined, which is abnormally thick because of the concavity of the undercut 30, cause the formation of cracks 36 near the bottom corners of the gate electrode 17. The cracks 36 extend well into the silicon in the channel region, effectively destroying the device.
FIG. 3 is a drawing made from an SEM (scanning electron micrograph) showing a cross section of a polysilicon gate structure, made by a salicide process on a wafer 30, in which the oxynitride ARC was removed with hot H3PO4 directly after polysilicon gate patterning. The photo was made after suicides 31A and 31B were formed respectively on the polysilicon gate 37 and the source/drain surfaces The polysilicon gate 37, has been undercut 32 by an H3PO4 etch which was used to remove a silicon oxynitride ARC. Silicon nitride sidewalls 33 were formed with an underlying pad oxide 34 which acts as a stress buffer. The pad oxide 34 and the silicon nitride sidewall 33 were formed after ARC removal. After the silicide forming anneal, a crack 36 developed in the undercut region and propagated well into the silicon channel region, destroying the device. The crack 36 was caused by thermal stresses in the nitride sidewall in the region of the undercut 32. wherein the nitride/oxide sidewall not only has a corner portion but also is thicker because of the undercut 32. The condition of high thickness in combination with increased concavity, caused by the undercut, results in a high shearing stress in this region making it prone to crack.
It would therefore be advantageous to have a method for protecting the sidewall from attack during the H3PO4 oxynitride etch, thereby preventing the undercutting. This would result in a more favorable contour as well as reduced sidewall thickness in the corner region, and consequently lower stress and elimination of crack formation. The present invention provides such a method.
Chan, U.S. Pat. No. 5,933,729 reduces the height of a vertical ONO (oxide/nitride/oxide) fence along non-vertical polysilicon sidewalls by the use of a fluorocarbon plasma etch in the formation of a flash memory device. This prevents residual angled ONO fence from shielding a polysilicon patterning etch and leaving polysilicon stringers. Wu, U.S. Pat. No. 6,033,956 forms a thin oxynitride/oxide layer on a polysilicon gate electrode which remains on the structure as the floating gate dielectric. Shih, et.al., U.S. Pat. No. 5,846,860 discloses a polysilicon wordline patterning process wherein additional oxide or nitride sidewall spacers are provided to define a buried contact.
It is an object of this invention to provide a method for removal of a silicon oxynitride ARC over a patterned polysilicon gate without damage to the gate sidewalls.
It is another object of this invention to provide a method for preventing undercutting of a polysilicon gate electrode prior to sidewall deposition.
It is yet another object of this invention to provide a method for preventing crack formation in sidewall structures formed on polysilicon gates.
These objects are accomplished by covering the exposed lateral sides of the polysilicon gate electrode with a thin protective silicon oxide layer prior to the removal of the ARC layer from the upper surface of the gate electrode. The silicon oxide is formed by RTO (rapid thermal oxidation) O2 or by plasma oxidation in O2 and H2O. After oxidation, the ARC is removed with hot H3PO4. The protective silicon oxide protects the lateral surfaces of the polysilicon gate from attack by the acid. Following implantation of the LDD regions, sidewalls formed. The method is particularly effective in preventing stress induced cracks in composite oxide/nitride sidewall which have feet and are more susceptible to stress induced cracks.